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Senior Design Verification Engineer

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Company
LanceSoft, Inc.
Job location
Canada, CA
Salary
Undisclosed
Posted
Hosted by
Adzuna

Job details

Pay rate is $92/hr on T4 Markham, ON (Oniste) KEY RESPONSIBILITIES: • Develop/Maintain tests for functional verification with UVM verification at the subsystem level • Build testbench components to support the next generation IP • Maintain or improve current test libraries to support IP level testing • Technically lead IPs in Control Fabric, • Have exposure to AXI protocol and Bootcode Verification • Provide technical support to other teams PREFERRED EXPERIENCE: • 5 years' experience required • Good at C/C++ • Good at SV and UVM • Good scripting knowledge in Perl, Ruby and Makefile • Familiarity with System Verilog and modern verification libraries like UVM ACADEMIC CREDENTIALS: • Bachelors (required) or Masters degree in computer engineering/Electrical Engineering
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