Note:- This is not a junior or entry level role candidate must have 6 years of industrial experience as Design Verification Engineer JOB DUTIES: • Participate in the functional verification of a Memory Controller IP and Subsystem. • Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. • Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. • Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. • Be familiar with hardware modeling and/or assertion-based verification methods. • Support all the parts of the verification lifecycle from planning to developing and maintaining code, debugging failures and supporting infrastructure like regressions and coverage. EXPERIENCE AND EDUCATION: UVM - System Verilog required 5 years’ work experience required Worked on complex SoC required Strong computer architecture knowledge required Prefer DRAM / Memory Controller experience B.S. in EE or Computing preferred