Other Jobs
Loading...

Digital Design (RTL) Engineer

Sorry, looks like this job is no longer open 😔

Check out other job openings on our job board!

View more
Company
Jobleads-US
Job location
Santa Clara, United States
Salary
Undisclosed
Posted
Hosted by
Appcast

Job details

Role: Digital Design (RTL) Engineer
Location: Santa Clara, CA - Remote work option allowed

Job Description:

Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog.
Experience in developing micro architectural documents from requirements specifications.
Experience developing designs from scratch.
Experience applying linting and other quality checking (QC) and basic verification of designs.
Experience supporting SoC designers in integration as needed.
Strong communication and collaboration skills.

Preferred:

  • Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
  • Candidate with design automation, scripting experience (Python) is preferable.

Responsibilities:

  • Develop HW architecture from specification documents.
  • Take complete responsibilities including writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and supporting physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
  • Develop and execute low power design (UPF/CPF).
  • Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc.
  • Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties).
  • Awareness of DFT concepts to be used to fix functional violations that may get introduced including DFT structures.
  • Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC, and STA. Debugging and fixing functional breaks.
  • Take ownership of tasks and drive tasks to closure.

Tools:

  • Synopsys/Cadence EDA Tools (Priority: 1)
  • LEC (Priority: 2)
  • STA/Constraints (Priority: 2)
#J-18808-Ljbffr
Get the freshest news and resources for developers, designers and digital creators in your inbox each week
Start Free Trial
Connect
RSSFacebookInstagramTwitter (X)
This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.
© 2000 - 2024 SitePoint Pty. Ltd.