Formal Verification Engineer

Formal Verification Engineer We are recruiting Formal Verification Engineers of all seniorities to work for a world-leading Semiconductor Company to join their dedicated Formal verification team working to deliver blocks for next-generation GPUs. This is a contract opportunity based in Manchester, UK. Our client is able to support visas and relocation where applicable. This is a great opportunity to work with some of the leading engineers in the industry and provides strong opportunities for future career progression. Key responsibilities for this Formal Verification Engineer position: Take an active role in shaping and developing how formal verification is deployed across our client's teams and projects globally. Promote, develop, and support advanced formal verification techniques. Build formal verification environments for critical areas of GPU design. Mentor junior engineers in formal verification. Develop new formal methodologies. Key Requirements: Strong experience in architecting/implementing formal verification environments. Experience in SVA and PSL. Experience working with industry-leading formal tools. eg. Cadence, Jasper Gold, Siemens EDA QuestaFormal, or Synopsys. Keywords: Formal Verification / Semiconductor / Semi conductor / Semi-conductor / GPU / SystemVerilog / System Verilog Assertions / Property Specification Language / Cadence / JasperGold / Siemens EDA / Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to tseu-recruit.com By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.com/about-us/privacy-notice/